White Electronic DesignsW3EG2MEFSU-D4
ADVANCED*
1GB – 2xMx DDR SDRAM, UNBUFFERED, FBGA
FEATURES
Fast data transfer rate: PC-2100, PC-2700 and
PC3200 Clock speeds of 133 MHz, 166 MHz and 200MHz Supports ECC error detection and correction Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#)
Programmable Read Latency 3 and 4 (clock) Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh
Serial presence detect (SPD) with EEPROM VCC = VCCQ = +2.6V ±0.1V (200MHz) VCC = VCCQ = +2.5V ±0.2V (133 and 166MHz) Gold edge contacts Dual Rank
JEDEC standard 200 pin, small-outline, SO-DIMM
package
•
PCB height option:
D4: 31.75 mm (1.25”)
* This product is under development, is not qualifi ed or characterized and is subject to change or cancellation without notice.
DESCRIPTION
The W3EG2MEFSU is a 2xMx Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of sixteen Mx8 DDR SDRAMs in FBGA packages mounted on a 200 pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.
NOTE: Consult factory for availability of:
• RoHS compliant products • Vendor source control options • Industrial temperature option
OPERATING FREQUENCIES
DDR400@CL=3
Clock SpeedCL-tRCD-tRP
200MHz3-3-3
DDR333@CL=2.5
166MHz2.5-3-3
DDR266@CL=2133MHz2-2-2
DDR266@CL=2.5
133MHz2.5-3-3
August 2005Rev. 0
1White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsPIN CONFIGURATION
PIN#SYMBOLPIN#SYMBOLPIN#SYMBOLPIN#SYMBOL
51VSS101A9151DQ421VREF
2VREF52VSS102A8152DQ46
53DQ19103VSS153DQ433VSS
4VSS54DQ23104VSS154DQ475DQ055DQ24105A7155VCC6DQ456DQ28106A6156VCC7DQ157VCC107A5157VCC8DQ558VCC108A4158CK1#9VCC59DQ25109A3159VSS10VCC60DQ29110A2160CK111DQS061DQS3111A1161VSS12DM062DM3112A0162VSS13DQ263VSS113VCC163DQ4814DQ6VSS114VCC1DQ52
65DQ26115A10165DQ4915VSS
16VSS66DQ30116BA1166DQ5317DQ367DQ27117BA0167VCC18DQ768DQ31118RAS#168VCC19DQ869VCC119WE#169DQS620DQ1270VCC120CAS#170DM621VCC71DNU121CS0#171DQ5022VCC72DNU122CS1#172DQ5423DQ973DNU123NC173VSS24DQ1374DNU124NC174VSS25DQS175VSS125VSS175DQ5126DM176VSS126VSS176DQ5527VSS77DNU127DQ32177DQ5628VSS78DNU128DQ36178DQ6029DQ1079DNU129DQ33179VCC30DQ1480DNU130DQ37180VCC31DQ1181VCC131VCC181DQ5732DQ1582VCC132VCC182DQ6133VCC83DNU133DQS4183DQS734VCC84DNU134DM4184DM735CK085NC135DQ34185VSS36VCC86DNU136DQ38186VSS37CK0#87VSS137VSS187DQ5838VSS88VSS138VSS188DQ6239VSSDNU139DQ351DQ5940VSS90VSS140DQ39190DQ6341DQ1691DNU141DQ40191VCC42DQ2092VCC142DQ44192VCC43DQ1793VCC143VCC193SDA44DQ2194VCC144VCC194SA045VCC95CKE1145DQ41195SCL46VCC96CKE0146DQ45196SA147DQS297NC147DQS5197VCCSPD48DM298NC148DM5198SA249DQ19A12149VSS199NC50DQ22100A11150VSS200VSS
W3EG2MEFSU-D4
ADVANCED
PIN NAMES
Symbol
A0-A12BA0, BA1DQ0-DQ63CB0-CB7CK0, CK0#CK1, CK1#CK2, CK2#CKE0-CKE1CS0#-CS1#
WE#, CAS#, RAS#DQS0-DQS8DM0-DM8VCCVCCSPDVREFVSSSCLSA0-SA2SDANCDNU
DescriptionAddress inputBank Address
Input/Output: Data I/Os, Data busInput/Output: Check BitsClock Input
Clock Enable InputChip Select InputCommand InputData StrobeData Write Mask
Supply: Power Supply: +2.5V ±0.2V
Supply: Serial EEPROM Positive Power Supply
Supply: SSTL_2 reference voltageSupply: GroundSerial Clock
Presence Detect Address InputInput/Output: Serial Presence-Detect DataNo ConnectDo Not Use
August 2005Rev. 0
2White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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White Electronic DesignsFUNCTIONAL BLOCK DIAGRAM
W3EG2MEFSU-D4
ADVANCED
CS1#CS0#DQS0DM0DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQS2DM2DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQS4DM4DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQS6DM6DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55 DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQ DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQDQS7DM7DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63 DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQ DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQDQS5DM5DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47 DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQ DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQDQS3DM3DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31 DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQDQS1DM1DQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15 DM S0# DQSDQDQDQDQDQDQDQDQ DM S1# DQSDQDQDQDQDQDQDQDQBA0, BA1A0-A12RAS#CAS#CKE0CKE1WE#BA0, BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE0: DDR SDRAMsCKE1: DDR SDRAMsWE#: DDR SDRAMs 120CK0CK0#120CK1CK1#VCCSPDVCCVREFVSSDDR SDRAMsDDR SDRAMsCK2CK2#SERIAL PDSCLWPA0A1A2120SDASA0SA1SA2SPD/EEPROMDDR SDRAMsDDR SDRAMsDDR SDRAMsNote: 1. All resistor values are 22Ω unless otherwise specifi ed.August 2005Rev. 0
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White Electronic DesignsW3EG2MEFSU-D4
ADVANCED
DC ELECTRICAL CHARACTERISTICS
PARAMETER/CONDITIONSupply VoltageI/O Supply VoltageI/O Reference Voltage
I/O Termination Voltage (system)Input High (Logic 1) VoltageInput Low (Logic 0) Voltage
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
SYMBOLVCCVCCQVREFVTTVIHVILVOHVOL
MIN2.32.30.49 × VCCQVREF - 0.04VREF + 0.15-0.3-16.816.8
MAX2.72.70.51 × VCCQVREF + 0.04VCC + 0.3VREF - 0.15
——
UNITSVVVVVVmAmA
CAPACITANCE
PARAMETER
Input/Output Capacitance: DQ, DQS,DMInput Capacitance: Command and AddressInput Capacitance: CK, CK#,Input Capacitance: CKE, S#
SYMBOLCI0CI1CI2CI3
MAX12472525
UNITSpFpFpFpF
August 2005Rev. 0
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White Electronic Designs0°C ≤ TA ≤ +70°C; VCC, VCCQ = +2.5V ±0.2VDDR400: VCC = VCCQ = +2.6V ±0.2V
W3EG2MEFSU-D4
ADVANCED
IDD SPECIFICATIONS AND CONDITIONS
MAX
PARAMETER/CONDITION
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mAOPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycleAUTO REFRESH BURST CURRENT:SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands
tREFC = tRFC (MIN)
SYMIDD0
DDR400 DDR333 DDR266 DDR266 UNITS@CL=3@CL=2.5@CL=2@CL=2.52475
2070
2070
1845
mA
IDD12745234023402115mA
IDD2PIDD2F
90990
90810
90810
90720
mAmA
IDD3PIDD3N
8101080
630900
630900
540810
mAmA
IDD4RIDD4W
27902790
23852295
23852295
21152025
mAmA
IDD5IDD6IDD7
4185905130
3510904545
3510904545
3330903960
mAmAmA
August 2005Rev. 0
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White Electronic DesignsW3EG2MEFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = VCCQ = +2.5V ±0.2V
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#CK high-level widthCK low-level widthClock cycle time
403
MIN-0.700.450.4567.50.450.451.75-0.600.350.35
335MAX+0.700.550.551313
MIN-0.750.450.457.57.50.50.51.75-0.750.350.35
262MAX+0.750.550.551313
MIN-0.750.450.457.57.5/100.50.51.75-0.750.350.35
265MAX0.750.550.551313
UNITSNOTESnstCK26tCK26ns39, 44ns39, 44ns39, 44ns23, 27ns23, 27ns27nstCKtCKns22, 23tCKtCKtCKnsnsnsnsnsns
SYMBOLMINMAXtAC-0.65+0.65tCH0.450.55tCL0.450.55
CL = 3tCK (3)510CL = 2.5tCK (2.5)CL = 2tCK (2)
DQ and DM input hold time relative to DQStDH0.40DQ and DM input setup time relative to DQStDS0.40DQ and DM input pulse width (for each input)tDIPW1.75Access window of DQS from CK/CK#tDQSCK-0.55+0.55DQS input high pulse widthtDQSH0.35DQS input low pulse widthtDQSL0.35DQS-DQ skew, DQS to last DQ valid, per group, per tDQSQ0.4access
Write command to fi rst DQS latching transitiontDQSS0.721.25DQS falling edge to CK rising - setup timetDSS0.20DQS falling edge from CK rising - hold timetDSH0.20Half clock periodtHPtCH,tCLData-out high-impedance window from CK/CK#tHZ+0.65Data-out low-impedance window from CK/CK#tLZ-0.65+0.65Address and control input hold time (fast slew rate)tIHF0.60Address and control input setup time (fast slew rate)tISF0.60Address and control input hold time (slow slew rate)tIHS0.8
+0.60+0.75+0.75
0.4
0.751.25
0.200.20tCH,tCL
+0.70
-0.700.750.750.8
0.5
0.751.250.200.20tCH,tCL
+0.75
-0.750.900.901
0.5
0.751.250.20.2
tCH, tCL
+0.75
-0.750.900.901
3016, 3616, 36121212
August 2005Rev. 0
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White Electronic DesignsW3EG2MEFSU-D4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
0°C < TA <+70°C; VCC = VCCQ = +2.5V ±0.2V
AC CHARACTERISTICSRAMETER
Address and control input setup time (slow slew rate)Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle timeDQ-DQS hold, DQS to fi rst DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge commandACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command periodACTIVE to READ or WRITE delayPRECHARGE command periodDQS read preambleDQS read postamble
ACTIVE bank a to ACTIVE bank b commandDQS write preamble
DQS write preamble setup timeDQS write postambleWrite recovery time
Internal WRITE to READ command delayData valid output window
REFRESH to REFRESH command intervalAverage periodic refresh intervalTerminating voltage delay to VDD
Exit SELF REFRESH to non-READ commandExit SELF REFRESH to READ command
SYMBOLtISStIPWtMRDtQHtQHStRAStRAPtRCtRFCtRCDtRPtRPREtRPSTtRRDtWPREtWPREStWPSTtWRtWTRNAtREFCtREFItVTDtXSNRtXSRD
0752004015557015150.90.4100.2500.4151tQH -tDQSQ
70.37.8
075200
0.61.10.6
MIN0.82.212tHP - tQHS
0.5070,000
4218607218180.90.4120.2500.4151tQH -tDQSQ
70.37.8
075200
0.61.10.6
403MAX
MIN0.82.212tHP - tQHS
0.5070,000
4015607515150.90.4150.2500.4151tQH -tDQSQ
70.37.8
075200
ns
tCK
0.61.10.6
335MAX
MIN12.215tHP - tQHS
0.75120,000
4020657820200.90.4150.2500.4151tQH - tDQSQ
70.37.80.61.10.6
262MAX
MIN12.215tHP - tQHS
0.75120,000265MAXns
UNITSNOTES12nsnsnsnsnsnsnsnsnsnstCKtCKnstCKnstCKnstCKnsµsµsns
22212118,191737374230, 4722, 23
August 2005Rev. 0
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White Electronic DesignsNotes
1. 2.
All voltages referenced to VSS
Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifi cations and device operations are guaranteed for the full voltage range specifi ed.Outputs are measured with equivalent load:
W3EG2MEFSU-D4
ADVANCED
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS.12. The refresh period is ms. This equates to an average refresh
rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed.13. The valid data window is derived by achieving other specifi cations
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55.14. Referenced to each output group: x8 = DQS with DQ0-DQ7.15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfi ed prior to the internal precharge command being issued.16. JEDEC specifi es CK and CK# input slew rate must be > 1V/ns (2V/ns differentially).17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain.18. tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)
condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfi ed.22. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).
3.
VTTOutput(VOUT)
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifi cations are guaranteed for the specifi ed AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).5.
The AC and DC input level specifi cations are defi ned in the SSTL_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level).
For slew rates less than 1V/ns and greater than or equal to 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns.Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
50ΩReference Point30pF6.
7.
8. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a specifi c voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ).9.
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turnaround.
August 2005Rev. 0
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White Electronic DesignsW3EG2MEFSU-D4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number
W3EG2MEFSU403D4-xW3EG2MEFSU335D4-xW3EG2MEFSU262D4-xW3EG2MEFSU265D4-x
Speed200MHz/400Mbps166MHz/333Mbps133MHz/266Mbps133MHz/266Mbps
CAS Latency
32.522.5
tRCD3323
tRP3323
Height*31.75 (1.25\") MAX31.75 (1.25\") MAX31.75 (1.25\") MAX31.75 (1.25\") MAX
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) • V endor specifi c part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualifi ed sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option
200-PIN DDR2 SODIMM DIMENSIONS
FRONT VIEW67.56 (2.66)3.81 (0.150 )MAX2.00 (0.079) R(2X)1.80 (0.071)(2X)20.00 (0.787)TYP6.00 (0.236)2.44 (0.096)1.10 (0.043)2.00 (0.079)0.99 (0.039)TYP0.46 (0.018)TYP63.60 (2.504)TYP0.61 (0.024)TYP31.75(1.25)PIN 199 PIN 1BACK VIEWPIN 200* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
August 2005Rev. 0
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White Electronic DesignsPART NUMBERING GUIDE
W3EG2MEFSU-D4
ADVANCED
W 3 E G 2M E F S U xxx D4 -x G
WEDCMEMORY
DDRGOLD
DEPTH (Dual Rank)
BUS WIDTH
x8FBGA2.5V
UNBUFFEREDSPEED (MHz)PACKAGE 200 PINCOMPONENT VENDOR
NAME
(M = MICRON)(S = SAMSUNG)G = RoHS COMPLIANT
August 2005Rev. 0
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White Electronic DesignsDocument Title
1GB - 2xMx DDR SDRAM, UNBUFFERED, FBGA
W3EG2MEFSU-D4
ADVANCED
Revision HistoryRev #
Rev 0
History
Created
Release Date
8-05
Status
Advanced
August 2005Rev. 0
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